A Parallel-Polled Virtual Output Queued Switch with a Buffered Crossbar

نویسندگان

  • K. Yoshigoe
  • K. J. Christensen
چکیده

* This material is based upon work supported by the National Science Foundation under Grant No. 9875177. Abstract Input buffered switches with Virtual Output Queues (VOQ) are scalable to very high speeds, but require switch matrix scheduling algorithms to achieve high throughput. Existing scheduling algorithms based on parallel requestgrant-accept cycles cannot natively support variable length Ethernet packets. In this paper, a Parallel-Polled VOQ (PPVOQ) architecture is proposed that natively supports variable length packets. Small amounts of FIFO buffering within a crossbar are used. Using simulation, the PP-VOQ with buffered crossbar switch is shown to have lower switch delay at high offered loads than an iSLIP switch for both cell and variable-length packet traffic. The PP-VOQ switch does not require internal speed-up or complex reassembly mechanisms. Priority mechanism implemented in both the iSLIP and PPVOQ switches are demonstrated to provide guaranteed rate and bounded delay for schedulable traffic.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Design and evaluation of a parallel-polled virtual output queued switch

* This material is based upon work supported by the National Science Foundation under Grant No. 9875177. Abstract Input-buffered switches with virtual output queueing require crossbar switch matrix scheduling algorithms. Existing scheduling algorithms are non-deterministic and are based on parallel and iterative request-grant-accept arbitration schemes. This presents challenges to flow-level sc...

متن کامل

A Four-Terabit Single-Stage Packet Switch with Large Round-Trip Time Support

We present the architecture and practical VLSI implementation of a 4-Tb/s single-stage switch. It is based on a combined input-and crosspoint-queued structure with virtual output queuing at the ingress, which has the scalability of input -buffered switches and the performance of output-buf-fered switches. Our system handles the large fabric-internal transmission latency that results from packag...

متن کامل

1 Architectures of Internet Switches and Routers

Over the years, different architectures have been investigated for the design and implementation of high-performance switches. Particular architectures were determined by a number of factors based on performance, flexibility and available technology. Design differences were mainly a variation in the queuing functions and the switch core. The crossbar-based architecture is perhaps the dominant a...

متن کامل

Output queued switch emulation by a one-cell-internally buffered crossbar switch

∗— Output-Queued (OQ) switching architecture is known to be of optimal performance amongst all queuing approaches. However, OQ switches were always known to lack scalability due to the high memory bandwidth constraints. Extensive research work showed that an OQ switch can be exactly emulated by a more scalable crossbar switch (i.e., InputQueued (IQ) switch) and a small speedup[9]. Unfortunately...

متن کامل

Routing on Input Queued Buffered Sparse-Crossbar Packet Concentrators

In this paper we characterize the features of good packet routing schemes for input queued sparse crossbar based packet concentrators and propose a polling based routing algorithm which achieves near optimal performance. It has been shown by the authors of this paper that the performance of an input queued packet concentrator with different input and output packet rates can be modeled by a GI/D...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2001